I have an issue which is inconsistent between the AMD implementation and the Nvidia one when related to creating descriptor set layouts. I have some shader code which implements two descriptor sets, and they have the layout(set=0) and layout(set=5) qualifiers respectively. The issue is when I create descriptor set layouts from these shaders, on AMD, I need to create a layout for sets 0 through 5, where the 1,2,3,4 are just empty with 0 binds. If I don't, the vkCreateXPipelines cause an access violation at some later stage. On Nvidia, I have to create only 0 and 5, otherwise the same function gets the same error. Just gathering from the documentation, the only 'required' behaviour for the set location qualifier is which descriptor set is bound where when calling vkCmdBindDescriptorSets, where in my case I would bind 0, NULL, NULL, NULL, NULL, 5. However, it seems like the pipeline linkage assumes the descriptor layouts tries to match the shader code by looking at the set qualifier in the shader code (index as-is on AMD, but indexed as incrementally on Nvidia) and use that as an offset into the pBindings used in the vkCreateDescriptorSetLayout and assume they match, but that's just my speculation.
However, this is an edge case where we have 'gaps' in the descriptor sets, and I can't find any specification on how this is supposed to work, but it would be nice to know what I can assume to be the right way.