Hi, I've got questions related to AMDs bus-addressable memory extension for OpenCL. We can do fast bi-directional data transfers with our custom FPGA board but the signalling is not yet working as it's supposed to be.
Our scenario is as follows: FPGA writes into GPU memory by passing the surface address that we got from making a GPU buffer resident. As far as I understood, we can also pass the marker address to the FPGA, let it update the value and the OpenCL run-time should be able to detect that writing finished. What we found out is, that clWaitForSignalAMD does not wait at all. No matter which value we use to wait for, the associated event finishes after some several hundred microseconds.
Second, do the marker values have to start at 0? The spec only says that they have to increase monotonically.