1 Reply Latest reply on Nov 3, 2015 2:44 AM by pinform

    Programming the GPU Command Processor directly

    tim.reago

      UPDATE 10/01/2015:

       

      A team of grad students at the University of Wisconsin (see miaow at GitHub) figured out:

       

      1) Instruction Memory is programmed via ports 0x50001000 and 0x50001004.

      2) SGPR Wavefront 1 is programmed via ports 0x50002000 thru 0x50002014.

       

      My understanding of the various copy, write and load Command Processor functions is that they are in the near ballpark of these above two port operations.

       

      Mantle does not allow the programmer to control the placement of objects in the cache hierarchy.  OpenCL and OpenGL, at the higher level, thus likely also do not allow the programmer to control object placement.  However, the lower level GPU documentation clearly identifies that placement is controllable.

       

      It thus appears that my question is related to AMD's Command Processor microcode instruction OPCODE's which would appear to be exclusive to AMD and AMD's documentation of that microcode.

       

      ORIGINAL 09/30/2015:

       

      For R9 SI series, some of the PM4 Type 3 IT_OPCODE's do not seem to be available anywhere.  The R6xx R7xx pdf had some of the codes, and I was able to find more on GitHub which were more specific to SI and Evergreen.  However there are a number of codes that are nowhere to be found.  The following list shows the codes that are still missing.  You can see from the list that these are critical to communicating with the Command Processor on the GPU.  The missing codes are likely to be in the range between 0x10 and 0x9F.  I saw an OpenGL flag OGL_PM4_CAPTURE_ENABLE and thought that might be a way to discover the codes, but no documentation on that either.

       

      enum PM4_TYPE3_IT_OPCODE

      {

          // Draw/Dispatch Packets

          DRAW_INDEX_MULTI_AUTO,

          DRAW_INDEX_INDIRECT,

          INDEX_BUFFER_SIZE,

          DRAW_INDEX_OFFSET,

          DRAW_INDEX_OFFSET_2,

          DRAW_INDIRECT,

          INDEX_BASE,

          DISPATCH_DIRECT,

          DISPATCH_INDIRECT,

       

          // State Management Packets

          LOAD_CONFIG_REG,

          LOAD_CONTEXT_REG,

          LOAD_SH_REG,

          ALLOC_GDS,

          SET_CONTEXT_REG_INDIRECT,

          LOAD_CONST_RAM,

          WRITE_CONST_RAM,

          WRITE_CONST_RAM_OFFSET,

          DUMP_CONST_RAM,

          SET_CE_DE_COUNTERS,

          INCR_DE_COUNTER,

          INCR_CE_COUNTER,

          WAIT_ON_DE_COUNTER,

          WAIT_ON_CE_COUNTER,

       

          // Command Predication Packets

          OCCLUSION_QUERY,

       

          // Synchronization Packets

          EVENT_WRITE_EOS,

       

          // Atomic

          ATOMIC,

          ATOMIC_GDS,

       

          // Misc Packets

          COPY_DW,

          COPY_DATA,

          ME_WRITE,

          CE_WRITE

      };