I am an AMD64 fan, and started to get in touch with it since 2005 when I was still in college. But recently I found something confusing me a lot. Somewhere, someone said "When AMD defined their AMD64 architecture as an extension of x86, they defined an enhanced version of PAE to be used while the processor was in 64-bit mode". But I think this description is not strictly correct. On page 130 of document http://support.amd.com/TechDocs/24593.pdf, it says
Long-mode page translation requires the use of physical-address extensions (PAE). Before activating long mode, PAE must be enabled by setting CR4.PAE to 1. Activating long mode before enabling PAE causes a general-protection exception (#GP) to occur.
The PAE-paging data structures support mapping of 64-bit virtual addresses into 52-bit physical addresses. PAE expands the size of legacy page-directory entries (PDEs) and page-table entries (PTEs) from 32 bits to 64 bits, allowing physical-address sizes of greater than 32 bits.
The AMD64 architecture enhances the page-directory-pointer entry (PDPE) by defining previously reserved bits for access and protection control. A new translation table is added to PAE paging, called the page-map level-4 (PML4). The PML4 table precedes the PDP table in the page-translation hierarchy.
Because PAE is always enabled in long mode, the PS bit in the page directory entry (PDE.PS) selects between 4-Kbyte and 2-Mbyte page sizes, and the CR4.PSE bit is ignored. When 1-Gbyte pages are supported, the PDPE. PS bit selects the 1-Gbyte page size.
Carefully reading the quoted words above, I understand that AMD64 architecture enhances the PAE paging data structures, but can we call this enhancement as an enhanced version of PAE? PAE is short for Physical Address Extension, introduced with Pentium Pro. It extends the 32-bit IA-32 instructions to access memory above 4GB indirectly. Paging extension is the chosen implementation, in other words, through paging extension, physical address has been extended from 32-bit to 52-bit, in the purpose of accessing even more physical memory beyond architecture limit but not changing the architecture. Under Long Mode, the architecture happen to change, 64-bit registers, 64-bit addressing capability. So Physical-Address Extension has already been set aside, only when some a day physical memory exceeds the size of space which 64-bit address could represent, it would be used again. When under compatibility mode, even though this enhanced paging method is applied, but it is no more PAE. The reason is obvious, because it is the 64-bit codes who manage paging under Long mode. From this point, one can hardly say that paging in Long Mode is an enhance version of PAE
Message was edited by: Aaron Janagewen