I am working on the low level interfaces of AMD kaveri APU. And I am studying the BKDG documents listed http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/
The first issue is about the linkage. The BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors is linked to the wrong document. Could anybody fix that on the website?
The second issue is about the NB (North Bridge) power management in the document BKDG for AMD Family 15h Models 30h-3Fh Processors. In 220.127.116.11.1, it says
• When the GPU is active :
• The high NB P-state is specified by D0F0xBC_x3F9E8[DpmXNbPsHi].
• The low NB P-state is specified by D0F0xBC_x3F9E8[DpmXNbPsLo].
When I check the specification of the register D0F0xBC_x3F9E8 (shown in the following figure), it says there are 8 bits in the domain of DpmXNbPsHi, DpmXNbPsLo, Dpm0PgNbPsHi and Dpm0PgNbPsLo, but only two bits are used to control the P-state of NB. This confuses me. So, which two bits are used to specify the P-state of NB?