11 Replies Latest reply on Sep 2, 2015 7:16 AM by logiotek

    Some issues on BIOS and Kernel Developer’s Guide (BKDG)

    qizhu.cs

      Hi,

       

      I am working on the low level interfaces of AMD kaveri APU. And I am studying the BKDG documents listed http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/

       

      The first issue is about the linkage. The BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors is linked to the wrong document. Could anybody fix that on the website?

       

      The second issue is about the NB (North Bridge) power management in the document BKDG for AMD Family 15h Models 30h-3Fh Processors. In 2.5.4.1.1, it says

       

           • When the GPU is active :

                • The high NB P-state is specified by D0F0xBC_x3F9E8[DpmXNbPsHi].

                • The low NB P-state is specified by D0F0xBC_x3F9E8[DpmXNbPsLo].

       

      When I check the specification of the register D0F0xBC_x3F9E8 (shown in the following figure), it says there are 8 bits in the domain of DpmXNbPsHi, DpmXNbPsLo, Dpm0PgNbPsHi and Dpm0PgNbPsLo, but only two bits are used to control the P-state of NB. This confuses me. So, which two bits are used to specify the P-state of NB?

      Screenshot from 2015-08-23 11:37:01.png

      Thanks.

        • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
          logiotek

          I am also working on some low level Kaveri code that requires changing some DPM parameters.

           

          Answer to your question is in section 2.5.4.1.1 of BKDG:

           

          2.5.4.1.1 Northbridge Dynamic Power Management (NB DPM)

          Northbridge Dynamic Power Management (NB DPM) dynamically changes which two of the four NB P-states

          are in use based on GPU activity as follows:

          • When the GPU is active :

          • The high NB P-state is specified by D0F0xBC_x3F9E8[DpmXNbPsHi].

          • The low NB P-state is specified by D0F0xBC_x3F9E8[DpmXNbPsLo].

          • When the GPU is idle and the timer timer specified by D0F0xBC_x3F9EC[Hysteresis] has expired:

          • The high NB P-state is specified by D0F0xBC_x3F9E8[Dpm0PgNbPsHi].

          • The low NB P-state is specified by D0F0xBC_x3F9E8[Dpm0PgNbPsLo].

          In addition, hardware forces the NB P-state to the active high or low NB P-state based on the GPU activity

          level.

          It depends on whether there is iGPU activity. Also you can define and enable only 1 NB P-state (NB_P0) and set that NB P-state for Hi/Lo of either D0F0xBC_x3F9E8 or D0F0xBC_x3F9E8 to fix the NB P-state completely irregardless of the workload. Most desktop motherboard BIOSes do this.

          • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
            logiotek

            Has to be the 2 lowest order bits from how other parts of documentation conform. DpmXNbPsHi[1:0] of D0F0xBC_x3F9E8 NB_DPM_CONFIG_1 [25:24]. I will do some testing tonight to confirm on my mobile Kaveri A10-7350B that has 4 NB P-States defined.

             

            First though, can you give me an insight on how to form the address needed to access D0F0xBC_x3F9E8 NB_DPM_CONFIG_1? I am using WinRing0 API that only has pciAddress and regAddress arguments and pciAddress is formed from device & function as indicated below. Up until now I've only worked with addresses like D18F5x170 (Northbridge P-state Control). How do I need to interpret D0F0xBC_x3F9E8?

             

            DWORD ReadPciConfig(DWORD device, DWORD function, DWORD regAddress)

            {

                const DWORD pciAddress = ((device & 0x1f) << 3) | (function & 0x7);

             

                DWORD result;

                if (!ReadPciConfigDwordEx(pciAddress, regAddress, &result))

                {

                    string msg = "cannot read from PCI configuration space (F";

                    msg += StringUtils::ToString(function);

                    msg += "x";

                    msg += StringUtils::ToHexString(regAddress);

                    msg += ")";

             

                    throw exception(msg.c_str());

                }

             

                return result;

            }

            Please advise.

              • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
                qizhu.cs

                Cool.

                 

                But in my case (A8-7600), I find that value of the register is quite strange. I can't understand that and I am not a expert on hardware issues so I didn't modify anything to be safe.

                 

                Please let me know if you have any findings.

                 

                Thanks.

                  • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
                    logiotek

                    I don't know if you saw my edited reply. Can you look at it again and advise on how to interpret register address D0F0xBC_x3F9E8? Looks like some form of indirect addressing. Up until now I've only worked with register addresses like D18F5x170. I am using WinRing0 library API for this.

                      • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
                        qizhu.cs

                        From BKDG, it says

                         

                        The index/data pair registers, D0F0xB8 and D0F0xBC, are used to access the registers at

                        D0F0xBC_x[FFFFFFFF:00000000]. To access any of these registers, the address is first written into the index

                        register, D0F0xB8, and then the data is read from or written to the data register, D0F0xBC.

                         

                        Hope it can help.

                          • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
                            logiotek

                            Thanks! Surprised they only mention it in one section in the middle of the guide. I'll let you know what I find tonight. Glad to know there's others doing similar work.

                            • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
                              logiotek

                              I performed some testing and here are my findings for Kaveri A10-7350B. I used my modified version of the original AmdMsrTweaker v1.1 CLI program to test this. And the output below is correct with reading all 8 bits of each field in D0F0xBC_x3F9E8. I should also mention that for GPU active DPM state DpmXNbPsHi/DpmXNbPsLo are correct to look up but for GPU idle DPM state the correct values are stored in NbPstateHi/NbPstateLo in D18F5x170 Northbridge P-state Control register. I hope this helps you. Now I'm trying to find where to read iGPU P-State information. If you happen to know you can point me to the right section in BKDG.

                               

                              AmdMsrTweaker v1.1

                               

                              .:. General

                              ---

                                AMD family 0x15, model 0x30 CPU, 4 cores

                                Default reference clock: 100 MHz

                                Available multipliers: 1 .. 21

                                Available voltage IDs: 0 .. 1.55 (0.00625 steps)

                               

                              .:. Turbo

                              ---

                                disabled

                                locked

                                Max multiplier: 33

                               

                              .:. P-states

                              ---

                                8 of 8 enabled (P0 .. P7)

                                Turbo P-states: P0 P1 P2

                                ---

                                P0: 33x at 1.125V

                                    NorthBridge in NB_P0

                                P1: 28x at 0.95V

                                    NorthBridge in NB_P0

                                P2: 25x at 0.925V

                                    NorthBridge in NB_P0

                                P3: 21x at 0.825V

                                    NorthBridge in NB_P0

                                P4: 19x at 0.8V

                                    NorthBridge in NB_P0

                                P5: 16x at 0.75V

                                    NorthBridge in NB_P0

                                P6: 13x at 0.725V

                                    NorthBridge in NB_P0

                                P7: 11x at 0.7V

                                    NorthBridge in NB_P1

                                ---

                                NB_P0: 12x at 0.9625V [ENABLED] [GPU Hi] [GPU Lo]

                                       Memory in M0

                                NB_P1: 11x at 0.925V [ENABLED]

                                       Memory in M0

                                NB_P2: 10x at 0.9V [ENABLED] [CPU Hi] [CPU Lo]

                                       Memory in M0

                                NB_P3: 8x at 0.8625V [ENABLED]

                                       Memory in M1

                                ---

                                M0: 800 MHz, MemClkFreqVal = 1, FastMstateDis = 0

                                M1: 333.3 MHz, MemClkFreqVal = 0, FastMstateDis = 0

                                • Re: Some issues on BIOS and Kernel Developer’s Guide (BKDG)
                                  qizhu.cs

                                  Hi,

                                   

                                  Your test is interesting. Is the AmdMsrTweaker available on Linux? Is there any way to manipulate the P-state of NB?

                                   

                                  Actually, I am also looking for methods to read the iGPU P-state and try to control it. However, I'm afraid you can not find any useful details from BKDG. About the power management of iGPU, only some general ideas and techniques are mentioned in the document. I suspect that the state of NB may affect the P-state (or frequency) of iGPU, because the iGPU controller is integrated in NB according to BKDG. You may try to confirm that. Some guys have told me that the GPU state is adjustable, but only with AMD internal tools.

                                   

                                  Anyway, I have moved my work to another heterogeneous platform, NVIDIA TK1 Jetson, on which GPU frequency, CPU frequency and Memory frequency can be adjusted manually in a much easier way. So I didn't work on APU any more due to the lack of frequency adjustment of iGPU. If you find out how to read and manipulate GPU P-state with public tools and methods, please let me know.

                                   

                                  Thanks.