Problems about OpenCL 2.0 on Kaveri APUs

Discussion created by acekiller on May 6, 2015
Latest reply on May 7, 2015 by maxdz8

Recently, I am happy to see the OpenCL 2.0 support (drivers and SDK) released by AMD on Kaveri APUs. However, I have some questions about those features that maybe someone could help me.


1) I am not sure how pipe is implemented on AMD platform. I mean, on other platform such Altera FPGA, pipe is implemented at hardware level (registers) so the performance is very good. On AMD platform, is it a hardware capability or just a software-level function provided by drivers?


We want to know more details about pipe implementation because we care about the performance. From some benchmarking results, we found that Pipe may be a cache favored component.


2) I noticed that there are quite a lot OpenCL 2.0 features (pipe, dynamic parallelism and so on) not supported on AMD CPUs. That is a pity for a real HSA platform. Is there a timetable for the support on the CPU also?

Hope anyone can help in this case.