0 Replies Latest reply on Dec 21, 2013 4:20 PM by sunsetquest

    documentation errors in the GCN instruction set guide

    sunsetquest

      Hello, I found some documentation errors in the AMD Sea Islands Instruction Set Architecture. (February 2013, Rev 1.0)  Some are minor typos and others are incorrect values.

       

       

      On Page 12-13 to Page 12-24,

      All the instructions from S_FF0_I32_B32(page12-13) to S_FLBIT_I32_I64(page12-24) have incorrect hex instruction number:

      Microcode SOP1 Opcode 17 (0x21)  <---  [17 != 0x21]
      ...
      Microcode SOP1 Opcode 24 (0x28) <---  [ 24 != 0x28]

       


      On Page 12-29,

      Incorrect hex value for S_SEXT_I32_I8 25 (0x29)  <--- [25 !=0x29]

       

      On page 12-142 and 12-143 the same hex value issue.

       

      On Page 12-145, these three instructions don’t have matching hex and decimal numbers

      DS_READ_B64…. 118   (0x74)
      DS_READ2_B64… 119   (0x75
      DS_READ2ST64_B64 … 1120(0x76)


      On Page 12-146,

      “maxw” should be “max”

       

      On page 12-146,

      Missing “)” for “(0xC9” 

       

      On page 12-147,

      Missing “)” for “(0xD2”

       

      On page 12-148,

      missing closing “)” for hex statements

      BUFFER_ATOMIC_XOR_X2 < - missing closing “)”
      BUFFER_ATOMIC_INC_X2 <- missing closing “)”
      BUFFER_ATOMIC_DEC_X2  <- missing closing “)” and should be 0x5D, not 0x5D0


      On Page 13-15,

      The bits on “SDST [21:15] enum(7)” overlap “OP [26:21] enum(8)” (bit 21 overlaps)

       

       

      On Page 13-15,

      The enum(8) in “OP [26:21] enum(8)” should be enum(5).

       

      On Page 13-39,

      “maxw” should be “max”

       

       

      On Page 13-41, enum should be 7 and bits should be 24:18

      "OP        [15:8]     enum(8)” should be “OP        [24:18]     enum(7)”

       


      On Page 13-44,

      “SOFFSET [63:56] enum(6)” should be  “SOFFSET [63:56] enum(8)”

       

      On Page 13-46,

      “Encoding [31:26] enum(7)” should be “Encoding [31:26] enum(6)”

       

      On Page 13-46,

      “Encoding [31:26] enum(7)” should be “Encoding [31:26] enum(6)”



      On Page 13-47,

      “SOFFSET [63:56] enum(6)” should be “SOFFSET [63:56] enum(8)” 


      On Page 13-51,

      “OP [24:18] enum(8)” should be “OP [24:18] enum(7)”

       

      On Page 13-51,

      “ENCODING [31:26] enum(7)” should be “ENCODING [31:26] enum(6)”


      On Page 13-52,

      “ENCODING [31:26] enum(7)” should be “ENCODING [31:26] enum(6)” 


      On Page 13-54,

      “ENCODING [31:26] enum(7)” should be “ENCODING [31:26] enum(6)”


       

      On Page 13-54,

      A “reserved 25 Reserved” is missing. (there is a 1 bit gap between OP and ENCODING)

       


      On Page 13-55,

      “VDST [63:56] enum(14)” should be “VDST [63:56] enum(8)” 

       

      Same Enum(7) error as above on…  (I’m just not writing these one out.)

       

      SOPC-OP

      SOPP-OP

      SMRD-OP

      VOP2-OP

      VOP3a-SRC0

      VOP3a-NEG

      VOP3b-SRC0

      VOP3b-NEG


      On Page 13-30, 

      [39:32] --> [40:32] 

      [48:40] --> [49:41]

      [57:49] --> [58:50]

      [59:58] --> [60:59]

      [63:60] --> [63:61]



      On Page 13-33, 

      [39:32] --> [40:32] 



      On Page 13-34, 

      [48:40] --> [49:41]

      [57:49] --> [58:50]

      [59:58] --> [60:59]

      [63:60] --> [63:61]


       

      BTW,  Please let me know if these minor errors should be emailed somewhere instead of the forums. In the document it states to report comments concerning this document to developer.amd.com.  Thank you.


      Also, Thank you AMD for publishing the ISA - it is much appreciated.  Other venders don't publish their GPU ISA.  I switched to AMD GPU's for this reason.