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Sequential work group sync.

Question asked by on Jun 19, 2012
Latest reply on Jun 19, 2012 by



I use hex editor to modify binary OpenCL kernels to modify some instructions. I've been enable to take advantage of some instructions like MUL_PREV, FLT_TO_INT_FLOOR (available in xyzw slots). There are few more such useful instructions that compiler doesn't use.


I'm looking for some information on how to use GROUP_SEQ_START and GROUP_SEQ_END instructions available on Evergreen architecture:

  1. Is it available on HD 6850 card?
  2. Does it require all threads within workgroup to reach it, like with GROUP_BARRIER instruction?
  3. Does it take any arguments?
  4. Does it require any additional information in binary file for it to work? Maybe it requires some setup by OpenCL runtime that is not accessible with current API?
  5. Does it span multiple ALU clauses?
  6. Where should it be placed: first/last instruction of ALU clause? Or can it be anywhere within a clause? What slot in VLIW it should use?


So far I was unable to make this instruction work. It doesn't cause any crashes and acts as NOP on my video card. I found no information on the web, so I thought writing a post myself. I understand I'm asking for some low level stuff, but since there's no official way of taking full potential of your video card, people have to resort to such hacks, as manually editing binaries.