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Hmm, one possible explanation would be:
64Kb 2-way means that every instruction modulo 32Kb ends up in the same cache line.
Assuming scenario in which you have three instructions (pieces of code): A (with address mod 64Kb equals to 0), B (different than A, also with address mod 64Kb equals to 0) and C (with address mod 64Kb equals to 32Kb), and assuming LRU policy, then following sequence of instructions will lead to observed behavior
Is it possible that you are experiencing such situation?
That's certainly a possibility. I did not look through all my code in CodeAnalyst to find other IC matches, since I had figured that a third bit of code would also show IC misses. I see from your scenario that this isn't necessarily so.
I'll look at my CA profile in more detail. In the meantime I have changed my code around, so I might not get this situation again. In the meantime I'll assume that the IC is really 2-way, and that my observations are consistent with that.