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Is Phenom instruction cache really 2-way associative?

Question asked by mrolle on May 18, 2012
Latest reply on May 21, 2012 by mrolle

I have some code that has two different functions at addresses that are separated by a multiple of 64 Kb, and CodeAnalyst tells me that they are both missing the instruction cache.  There is other code at matching addresses modulo 64 Kb, but it is not being run in this particular test.  Actually, CodeAnalyst is not reporting any IC misses anywhere else in the program.  If there were 3 different programs competing for the cache space, then I should expect to see all 3 of them getting IC misses.  The miss latency being reported is 17 cycles.


This behavior seems to imply that the IC is not 2-way associative, as it is advertised to be.


I hope that I am misunderstanding something here about the IBS event being reported.  I would hate to think that the IC is only 1-way instead of 2-way.  Assuming it is really 2-way, then I have the problem of explaining the IC misses and figuring out how to avoid them.


Anyone have some experience with this issue and can help me?