2 Replies Latest reply on May 21, 2012 11:47 PM by mrolle

    Is Phenom instruction cache really 2-way associative?


      I have some code that has two different functions at addresses that are separated by a multiple of 64 Kb, and CodeAnalyst tells me that they are both missing the instruction cache.  There is other code at matching addresses modulo 64 Kb, but it is not being run in this particular test.  Actually, CodeAnalyst is not reporting any IC misses anywhere else in the program.  If there were 3 different programs competing for the cache space, then I should expect to see all 3 of them getting IC misses.  The miss latency being reported is 17 cycles.


      This behavior seems to imply that the IC is not 2-way associative, as it is advertised to be.


      I hope that I am misunderstanding something here about the IBS event being reported.  I would hate to think that the IC is only 1-way instead of 2-way.  Assuming it is really 2-way, then I have the problem of explaining the IC misses and figuring out how to avoid them.


      Anyone have some experience with this issue and can help me?





        • Re: Is Phenom instruction cache really 2-way associative?

          Hmm, one possible explanation would be:


          64Kb 2-way means that every instruction modulo 32Kb ends up in the same cache line.


          Assuming scenario in which you have three instructions (pieces of code): A (with address mod 64Kb equals to 0), B (different than A, also with address mod 64Kb equals to 0) and C (with address mod 64Kb equals to 32Kb), and assuming LRU policy, then following sequence of instructions will lead to observed behavior




          Is it possible that you are experiencing such situation?

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            • Re: Is Phenom instruction cache really 2-way associative?

              That's certainly a possibility.  I did not look through all my code in CodeAnalyst to find other IC matches, since I had figured that a third bit of code would also show IC misses.  I see from your scenario that this isn't necessarily so.


              I'll look at my CA profile in more detail.  In the meantime I have changed my code around, so I might not get this situation again.  In the meantime I'll assume that the IC is really 2-way, and that my observations are consistent with that.