I seem to recall that most (all?) discrete GPUs have 16 wide SIMD engines and thus use 64 wide wavefronts (4 cycles per wavefront), but that some of the lower end / embeded GPUs actually have 8 wide SIMD engines (for example the 40 cores GPUs) and thus have 32 wide wavefronts. I can't however find any references to the point at the moment and was wondering if anyone can verify / disprove the notion and can hopefully give me some references either way.
This is true for all GCN hardware, but on some older low-end chips the wavefront size is 16/32.
You can figure this out by looking here:
In appendix D, take the number of stream cores and divide it by the number of compute units and multiple by 4, that is the wavefront size.