USWC and discrete GPU

Discussion created by Raistmer on Sep 17, 2011
Latest reply on Sep 18, 2011 by genaganna
why only APUs mentioned?

USWC - Host memory from the Uncached Speculative Write Combine heap can be accessed by the GPU without causing CPU cache coherency traffic. Due to the uncached WC access path, CPU streamed writes are fast, while CPU reads are very slow. On Fusion devices, this memory provides the fastest possible route for CPU writes followed by GPU reads.

And what will be fastest for Discrete GPU, provided CPU can perform streamed writes for data buffer?