DRAM Accesses vs. Read and Write Bandwidth

Discussion created by on Dec 2, 2010

Using the document "Basic Performance Measurements for AMD Athlon64...", I measured DRAM_ACCESSES (0xE0, mask 0x3F),  NORTHBRIDGE_READ_RESPONSES (0x6C, mask 0x1F) and OCTWORD_WRITE_TRANSFERS (0x6D, mask 0x01). 

The document would suggest that reads + writes = DRAM bandwidth. However, I have found that in some cases I will see reads + writes <= 0.8 * DRAM bandwidth (even where DRAM bandwidth is > 10GB/s). In other cases, reads + writes > DRAM bandwidth. Only in a few cases are these approximately equal.

I know that there are prefetches and page misses that are probably not accounted for in the read and write bandwidth, but how can I interpret these results? Is my interpretation of what these counters mean incorrect?