I would like to find out how the mapping between the L2 and L1 cache slots is defined on the Athlon/Opteron hardware.
In other words, what I’m interested in establishing is whether the respective allocations of cache lines on the L2 cache memory for L1 (D) and L1 (I) caches follow a rigid 50/50 split (i.e. 256KB + 256 KB) or the allocation varies according to respective sizes of the code and data segments of the executing program.
My apologies if I’ve overlooked the obvious - any pointers to relevant literature will be appreciated and thanks in advance for your help.
The L2 cache is strictly a 'spillover' cache for data evicted from L1. As such, there is no 50/50 D/I split. It's all data in an n-way associativity.