2 Replies Latest reply on Apr 26, 2010 4:52 PM by alexg

    Can Radeon handle sparse matrices?

      non-coalesced memory access

      I'm intereted in multiplying a sparse matrix of size 2000x2000 with 5-10% non-zero elements by a dense matrix of size 2000x20 to 2000x100.

      I've been told that since sparce matrices require non-coalesced memory access, Radeon won't be able handle them (efficiently?). Is this correct?

        • Can Radeon handle sparse matrices?

          That depends. You could use Images on input to provide caching, which isn't supported in the current SDK but will be in the near future. If you choose a blocked matrix layout you could have small blocks of 4 or maybe 16 floats which are read at a given point in the matrix and which will mean that each memory read will be a reasonably efficient vector read.

          In your case you can probably have multiple whole columns of the dense matrix in LDS at once. You can then read whole rows, or even overlapping multiple rows, of the sparse matrix and multiple them random-access-style with the dense matrix. That assumes your storage is some CSR-based structure. If you then have a blocked CSR you could multiple by multiple dense rows at once getting even better use of LDS. It really depends on the properties of your sparse matrix.

          Sparse matrix storage formats always have to be tweaked to get good performance on any architecture, and the AMD GPUs are no different in that. Your question depends on too many parameters. Don't think so much about whether the architecture can do it but rather how you want to define your sparse data structure to ensure that the architecture can do it.