Hi I have seen Siggraph Asia OCL course and I can't believe here some at AMD not publish a link to it..
http://sa09.idav.ucdavis.edu/
now I have some questions:
First a good presentation from AMD is not online:
Generic OpenCL Optimizations (Jason Yang, AMD)
someone at AMD can publish presentation somewhere.. seems good to learn..
also from:
OpenCL C++ Bindings (Jayanth Gummaraju, AMD)
seems AMD has a nice OpenCL Ocean demo using FFTs..
AMD is going to publish code in SDK for users learning about a complete app using OGL interop.. or better: here and now as a gift for forum readers 🙂
Also from
OpenGL Interop Examples (Timo Stich, Nvidia)
altough this is from Nvidia guy stuff :-))
Regarding OGL interop: clGetGLContextInfoKHR seems of much use..
for example you can use ocl ogl interop but I have an Nvidia and AMD card (Windows 7)
and I set for example default Nvidia monitor and OpenCL AMD ICD is loaded if I create a OGL context by default will use Nvidia OGL driver and then I create a context with OGL interop this will use AMD OCL driver and in fact AMD is joking us as it will work (so native interop (in device memory) is not working and going trough system mem).. but using the other way OGL AMD context and OCL nvidia context will return an error in clcreatecontext..
I can get info from this situations or others using:
clGetGLContextInfoKHR
the problem is that is not in .lib files and not exported in Khronos ICD DLL
but is in cl_gl.h file shipped with AMD..
Altough this is AMD forum Nvidia situation is worse..
in fact they don't ship a cl_gl.h with clGetGLContextInfoKHR definition and their Khronos older ICD don't expose it..
So when it's going to be released a SDK with clGetGLContextInfoKHR function..
Last is from:
AMD IHV Talk - Hardware and Optimizations (Jason Yang, AMD)
Questions:
how much of hardware integer instructions in slide 13 are exposed currently..
AMD is working to enable through extensions?..
I'm interested in this (as at least some of this aren't DirectCompute supported):
*Reverse bits
*Integer Add with carry
*1bit prefix sum on 64b mask. (useful for compaction)
*Shader Accessible 64 bit counter
At least in isa docs I can find info about two first but I'm interested in
1bit prefix sum on 64b mask. (useful for compaction)
how to use it?.. some cal example? more info please..
Also more info on "Shader Accessible 64 bit counter"..
what isa instruction?
Search isa docs
ALU_SRC_TIME_HI: Upper 32 bits of 64-bit clock counter.
228 ALU_SRC_TIME_LO: Lower 32 bits of 64-bit clock counter.
At least for Integer add with carry we have a CUDA enabled compiler:
http://www.mpi-inf.mpg.de/~emeliyan/cuda-compiler/
And what about dx11 based ones?: find first bit, etc..
Also as said in an earlier post: 24 bit integer MUL,MULADD
well this isn't generated altough using mad24 ocl
so I don't know if:
– Heavy use for Integer thread group address calculation
is correct in slide..
