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gmtan
Journeyman III

input/output remote system memory

A shader kernel can directly accesses remote system memory. The memory operations are automatically performed by DMA engine in memory controller? For example, o1 is defined as a buffer in remote system memory. A operation of "add o1, r0, r1" implies a DMA operation?

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frankas
Journeyman III

Originally posted by: gmtan 

A operation of "add o1, r0, r1" implies a DMA operation?

 

add instructions are part of ALU clauses, and operate on registers, memory access happens in memory fetch clauses, but I am not all thet familiar with the mechanics of those to try and answer your question.

But a general observation is that graphics memory is the fastest to operate on, and from the CPU side acces to graphics memory come in 3 flavours.

Cached / Uncached / DMA.

Cached and uncached memory is graphics memory that is mapped into the CPUs adress space, and DMA transfers can be set up to copy between the two memory systems.

As for the GPU accessing main memory directly (which would be slow) ... I can hardly see why that would ever be desirable.

 

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add instructions are part of ALU clauses, and operate on registers, memory access happens in memory fetch clauses

 

IL is only an intermediate language. Each IL instruction is not necessarily mapped to one ISA instructions. In this case, add will be performed on general purpose registers. The result will be written to the memory later by other ISA instructions.

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I'm wondering that when the DMA transfers are REALLY performed? Is it involved with PCIE transfer? 

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