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jhuell
Journeyman III

Page Walk Cache on NPT

Virtualization archiecture

As you know, AMD-V has some versions like NPT only or NPT with Page Walk Cache. Is there somebody who knows which one has NPT with Page Walk Cache? 

Thanks

 



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mrolle
Adept II

Let me tag on this with a question of my own...

Is it true that all the AMD processors (or at least K8 onward) have a page walk cache, and even if only some models have it, what are the specs?

I'm writing applications that access more data than can be held at one time in the TLB, and the page walk cache would affect the cost of TLB misses, and thus could affect the overall algorithms.

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Hello jhuell,

AMD-V™ Rapid Virtualization Indexing (RVI, also known as “Nested Paging” or “Nested Page Tables&rdquo was introduced with the first  AMD Quad Core Opteron™ processor (known as “Barcelona&rdquo and, as noted in an AMD-V Nested Paging  white paper (section 4.2.6, http://developer.amd.com/assets/NPT-WP-1%201-final-TM.pdf), RVI utilizes the Page Walk Cache.  All AMD Quad-Core and Six-Core Opteron processors feature AMD-V with RVI.  You can review processor specifications at http://www.amd.com/us/products/Pages/processors.aspx for more information on AMD-V with RVI.

Thank you.

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Hello mrolle,

All processors since K6 have had some sort of PWC, and PWC characteristics vary between processor models.  Regardless of the processor model, PWC hit rates tend to be very high and in general we do not believe there is much benefit in trying to optimize applications for these differences.  Hence we are not prepared to publish such details.

Thank you.

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