1 Reply Latest reply on Oct 5, 2009 7:01 PM by Randy

    Does the processor have special behaviour for multiple prefetch on same cache line ?

    DevProg
      Does the processor have special behaviour for multiple prefetch on same cache line ? for example: mov eax,[ptr] prefetchnta [eax] prefetchnta [eax+4] prefetchnta [eax+8] prefetchnta [eax+12] prefetchnta [eax+16] prefetchnta [eax+20] Does the Load buffer allocate entries of these prefetches?