DevProg

Does the processor have special behaviour for multiple prefetch on same cache line ?

Discussion created by DevProg on Sep 29, 2009
Latest reply on Oct 5, 2009 by Randy
Does the processor have special behaviour for multiple prefetch on same cache line ? for example: mov eax,[ptr] prefetchnta [eax] prefetchnta [eax+4] prefetchnta [eax+8] prefetchnta [eax+12] prefetchnta [eax+16] prefetchnta [eax+20] Does the Load buffer allocate entries of these prefetches?

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