2 Replies Latest reply on Oct 25, 2009 3:58 AM by aehusain

    Performance Counter selection!

    aehusain
      To evaluate Cache, RAM and disk usage parameters!

      Dear All,

      I am trying to select performance counters to measure CACHE, DISK and Memory utilization in AMD Opteron systems.

      Can I expect to get to get usage using following performance event monitoring:

      1. Cache:  Data Cache Accesses and Instruction Cache Acceses

      2. Memory: Dram Accesses (with unit mask 0x01 for Page hit)

      3. Disk: There are two components: dma and non dma

      a. Dram Accesses with unit mask 0x02 for Page Miss

      b. hypertransport link0 with unit mask 0x02 for dma'ed data

      If anybody has done any of these measurement, please comment if there is some gap in my understanding.

      I tried to run a sample copy script (copying a large image 1 Gb in loop) and analyzing the above events, I was not able to conclude much from it.

      Thanks for your suggestions!

      Regards,

      Ata

       

        • Performance Counter selection!
          pdrongowski

          Hi Ata --

          I was trying to read between the lines to determine what performance questions you were trying to answer.

          Performance counter events can definitely measure data cache and instruction cache accesses (Event selects 0x040 and 0x080). You can also measure the number of DRAM accesses (Event select 0x0E0). I think this is consistent with what you have mentioned in your posting.

          However, here's a few fine points. It sounds like you would like to measure page faults and disk I/O. Unfortunately, it's hard to infer information about performance at this level of abstraction through the use of performance counter events. You will probably need to use OS-level monitoring tools (like top on Linux or the Task Manager, etc. on Windows) to look at page faults and disk I/O.

          The "page hit" and "page miss" refer to memory controller/DRAM pages which are a different concept than virtual memory pages. It's confusing, but modern memory controller design has the concept of open and closed pages which is separate from the notion of virtual memory pages.

          Hope this helps!

          -- pj