All of our chipsets behave the same way. 128B for DMA writes. 4K for DMA reads. 64B for DMA read completions. Host read/write requests are limited to 64B.
After three years, is this still true? All of AMD's chipsets including the new ones still behave the same way? 128B for DMA writes, 4KB for DMA reads, 64B for DMA read completions. Host read/write requests are limited to 64B.
I am assuming this is your convention?
DMA write - PCIe MWr from Device to Host
DMA read - PCIe MRd from Device to Host
DMA read completion - read completion from Host to Device
I find that all AMD chip sets work in the same manner. I understand that the payload size is not much but I need to know what supports different payload sizes