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[Brane2]

I can find it only for 0Fh and 11h families...

I'm unstisfied with memtest86+ and would like to optimize,rework and expand it, but in order to da that properly I neeed more info about extra hardware on CPU ( PLLs, memory controller, HT links etc).

"BIOS and Kernel Developer's Guide" contains that kind of info, but version for Phenom doesn't seem to be available...

It would be nice if I could get ACC- related info, but I suppose this is deeply in the "wet dreams" area...

Can anyone help ?

[stroia]

The BKDG for family 10h is available on this page http://developer.amd.com/DOCUMENTATION/GUIDES/Pages/default.aspx.

thanks,

sharon

[Brane2]

Bullseye. Thanks.

BTW: Was that document there all along, or did you add it after my request ?

I could swear I couldn't find it anywhere and now that it is there, my Firefox says it has seen that document before ( link is gray ).

Which kind of trigerred slight "where are my pills ?" attack.

Is this some new, updated version ?

[stroia]

Nope, not a new version.  It was there all along.  Maybe the fact that it was grey on your system tricked you into missing it... Not sure, but that happens to the best of us

-Sharon

[Brane2]

Well, thanks.

Is there any chance on seeing ACC-related material ?

It need not be in full form, just what I need to write in which register in order to activate ACC and to set it per core- just as I can do manually in BIOS...

[stroia]

I'm not sure what ACC is exactly, can you elaborate?  I'll ask one of our engineers, but I need to know a little more about what exactly I'm asking for.

thanks,

sharon

[Brane2]

I think Wikipedia puts it best:

ACC=Advanced Clock Calibration, a technology present in some of the AMD 700 Southbridge chip series that enables achievement of higher CPU clock speeds for the K10-based processors

One part of ACC is in conforming SouthBridge chip ( like SB750 and later), other is in conforming CPU ( Like Phenom I or II ).

SB chip can regulate certain parameters in CPU through special interface ( reportedly 6 pins ), which can enable CPU to be able to overclock to higher frequencies or to use less power at nominal frequencies.

ACC can be regulated on each core separately from the others.

As I understand, much of whole shebang is kept in secret, but it would be nice to know at least the bit, which would enable me to make boot-time or Linux kernel driver for setting/testing it.

I have sifted through aforementioned "BIOS and Kernel Developer's Guide" and other documents, SB7xx documentation etc, but ACC is not even mentioned anywhere...

[stroia]

I searched through some of our upcoming public RS780 documentation and didn't see anything.  Let me check with some of our engineers and see what I can find out.

[stroia]

It's looking like this information is very secret.  I can't find it in any NDA BKDG documents or other NDA docs.  But, I've sent a question to some of our very bright BIOS developers to see if they have the information and if they have it, I have to get clearance to share it with the public... so, stay tuned, but be prepared for the likelyhood that I won't be able to share it.

[stroia]

Here's the response from our BIOS engineers:

"Due to the nature of ACC a system reboot is required to toggle it, therefore ACC cannot be enabled/disabled at runtime.  All systems that implement the ACC feature do it with a BIOS control, any other agent attempting to modify its state would conflict with the BIOS which regains control of the system when the required reboot occurs.  I am sorry but this feature cannot be easily be controlled by a user application"

[Brane2]

It would be still benefitial to have data about it for projects like coreboot ( open source BIOS - http://www.coreboot.org/Welcome_to_coreboot ), but that is not my concern right now.

You've helped me plenty.

Thanks.