6 Replies Latest reply on Jul 16, 2009 9:00 AM by Brane2

    Tiled/Linear Memory Addressing

    TST

       

      I would like to know about memory addressing format of frame buffer and depth buffer and texture.

      Does HW (RV770) support tiled based addressing of frame buffer and depth buffer and  texture ?

      Please let me know how to set it.

      If not, whitch is the default setting ?



      Thanks.

        • Tiled/Linear Memory Addressing
          avk

          Have you read R700 ISA document? If are there any answers exist, they are in that PDF-file.

            • Tiled/Linear Memory Addressing
              TST

               

              avk, thanks for that PDF. but I would like to know how to set tiled memory layout using DirectX, sorry. Can anyone AMD answer this ? Regards.


                • Tiled/Linear Memory Addressing
                  bridgman

                  The hardware definitely supports tiled or linear accesses, but AFAIK tiling is managed by the graphics/video drivers and the underlying memory manager. Normally surfaces used for 3D operations would be tiled for best performance.

                  I don't believe tiling is directly controllable through the DirectX API.

                • Tiled/Linear Memory Addressing
                  Brane2

                   

                  Originally posted by: avk Have you read R700 ISA document? If are there any answers exist, they are in that PDF-file.

                   

                  Great. BTW, is there any link on official pages to that file ?

                  I couldn't find it anywhere on developers pages. Even saerching for it found just your post.

                  I tried to see if there are other accessible goodies in that map, but system won't let me in, because my blood is not green enough.

                  Is there a way to get access permission for that kind of goodies for us mere mortals ?

                   

                   

                   

                    • Tiled/Linear Memory Addressing
                      bridgman

                      The document is linked off the "Stream SDK" page. Just go to www.amd.com, click on "SW Developers", then click on "ATI Stream SDK". The document link is near the bottom.

                      http://developer.amd.com/GPU/ATISTREAMSDK/Pages/default.aspx

                      That said, unless you are writing your own driver I don't think you will be able to set tiling yourself anyways.

                      If you are writing your own driver there is some information for driver developers at http://www.x.org/docs/AMD in the R6xx-3D-Registers.pdf document, not sure if we have that mirrored on amd.com yet. We are supporting two modes; linear and  ARRAY_2D_TILED_THIN1, which is an 8x8 array of 8x8 smaller tiles, ie 4096 pixels per tile. Tiling is currently supported on the Z buffer (DB) and render target (CB).

                       

                        • Tiled/Linear Memory Addressing
                          Brane2

                           

                          Originally posted by: bridgman The document is linked off the "Stream SDK" page. Just go to www.amd.com, click on "SW Developers", then click on "ATI Stream SDK". The document link is near the bottom.


                          It is interesting that link "SW Developers" is not present on all versions of the www.amd.com.

                           

                          When I go to www.amd.com, it redirects my browser to "http://www.amd.com/uk/Pages/AMDHomePage.aspx" and there is no aformentioned link.

                           

                          But if I change that "/uk/" part of the URL with "/us/", I get page with "SW Developers" link...