godsic

Microcode on-chip optimization

Discussion created by godsic on Apr 7, 2009
Latest reply on Apr 23, 2009 by binutils
TO STORIA!

Basically, I am a little bit tiered to write such topics in AMD forum, because nobody read them and even does not know what this about! But I am always was an AMD/ATI fan and I just try to help AMD to improve their CPU! I have a lot of experience in ASM on Z80 CPUs that is why I have a lot of ideas how to improve modern CPU! Because out-of-order execution is not very efficient in modern scientific (calculation intensive) application! I am several times try to contact AMD and tell them about, but this is impossible thing to do! I have no time to write papers in relate journals to prove my concept to developers! I hope AMD processors developer team is very experienced and can understand my ideas and can try to check them for consistency.

1: Can you implement on-chip microcode optimization - I mean - if CPU fetch more than 1 instruction for decoding and build sequence of microcode (without vector path and direct path) after it can analyze this sequence and determinate if it can skip some ops or replace them with more efficient sequences!!!! (it can be done using templates in on-chip ROM for most frequent instruction sequences)!

2: Can you implement SIMD like microcode - I mean - if CPU fetch more than 1 instruction it can use SIMD microcode to decode instruction sequences! For example instruction sequence need to send values or 4 registers into other 4 registers - in modern architecture it will be 4 DirectPath ops, in proposed architecture it will be on SIMD microcode op! It can be realized similar to 1.

Best wishes,

Mykola Dvornik.

Magnonics Group

Physics Depratment

University of Exeter.

godsic@ukr.net

mad211@ex.ac.uk

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