So, if I read the documentation correctly, there are 5 stream cores per thread processor. All five them can perform one integer/floating point operation per cycle, with the T-unit additionally being able to perform transcendental operations. However, there is no float5 construct and registers are only 128 bit. Does that mean the following can be issued in a single VLIW word?
add r2, r0, r1
add r5.x, r4.x, r3.x