Wavefronts Question

Discussion created by ryta1203 on Feb 12, 2009
Latest reply on Feb 18, 2009 by ryta1203
Are wavefronts put in the run-queue, as one presentation suggests OR are wavefronts run in parallel (some-type of switching mechanism or what?) as some other presentation suggests??

AMD is still having a hard time getting all of it's terminology on the same page it seems. I have VERY curious about this question.

If Wavefronts are put in a queue, then that suggests that they are not run in parallel. If they are run in parallel, what purpose does the queue serve? A queue by nature is FIFO and therefore should not serve as some switching structure.

The docs on this are a little confusing, IMO. I have also looked at a few presentations and they some to conflict, or at least to me (I'm sure they make perfect sense to people who already know how the hardware works).

The runtime suggests that the lower the GPR the better, which then suggests that the wavefronts are running in parallel (switching) to hide memory latency (on top of the threads in a quad running in parallel to hide memory latency. So is this the same mechanism working on two fronts?? (threads in a quad and wavefronts?)