Hello, Mr. Shamsundar,
This looks like a bug in Valgrind's diassembler.
While those instruction code bytes are indeed very odd looking, they are valid combinations.
You are correct that the REP prefixes only cause repeats on the string instructions. When they are applied to an instruction like fmul, they have no effect. That does not make the code byte sequence invalid, however. Any x86 processor from AMD, Intel or another manufacturer will simply go ahead and execute the fmul instruction, ignoring the nonsense prefix.
As an aside, the codes F3 and F2 have completely different uses when they are part of an SSE instruction. When I first saw your post, I thought that might be the case here, but those code bytes are always ... F3 0F ... or ... F2 0F ....
In this case, it looks like the REP prefixes were inserted to pad the instructions and make them longer. This was probably someone tuning the code to get the best possible performance on a particular processor. In some cases, simply changing the alignment of the instructions in memory might have made the difference between the instruction decoder dispatching three instructions in a cycle instead of just two. It's quite possible that this is an old optimization for an obsolete processor, but it hasn't been removed because it has no performance effect on other processors.
Some compilers will insert nonsense REP prefixes in order to align code, like aligning the top of a loop to a cache boundary. You can align instruction codes by inserting NOPs, too, but even NOPs have to be treated as instructions by the cpu's instruction decoder.
The language in the AMD Architecture manuals: "should only be used with such string instructions" is probably misleading.
Thanks. Your response clear it up for me.