7 Replies Latest reply on Mar 25, 2009 11:04 AM by indi123

    Full docs for CPUs chipsets and GPUs ?


      I was searching through AMD's docs and but couldn't find anything for:

      1. K-8 & K-10 internal registers, governing IMC settings, various frequencies and multipliers etc.

      I was reading through memtest86+ code ( RAM test utility ) and I think it could be done _much_ better if one had access to such data.

      Also, one could stress CPU cores while accessing RAM and tweak freq multipliers, RMA timings etc to either asess OC borders or stability of the machine.

      2. chipset data ( especially GX790 with sideport, FX790 and SB750 ).

      I seek to improve various ways of doing things in Linux and FX790 with inbuilt GPU and sideport seems very good foundation for many tricks.

      For example, RAID-6 P and Q syndrome calculation rutines in kernel seem very optimised, but even so they can be slow, especially when two disks are down and everything has to be fully reconstructed.

      Employing GPU shaders for such taks seems like a very good idea.

      Also, console as well as graphic X11 terminal ops could be at least partially done in GPU as well as some encryption/decryption algorithms, so one could have encrypted HDD disks/partitons/files without much CPU overhead , reduced bandwidth or extra latency...

      It seems to me that with a bit of right code RS790 could fly...

      3. Discrete GPU chipset data.

      Same as for point 2, albeight a bit more computing oriented. nVidia's CUDA seems to be fine, but it's not immediately obvious to me how one would use it in kernel code and how could it be integrated into display functions seamlessly. AMD had CTM program for a while and after it vanished I kinda hoped that specs are to be "opensourced" so CTM would be kid of pointless from that point on...

      Is there some way to get to such data without sacrificing eldest daughter and a goat ?

        • Full docs for CPUs chipsets and GPUs ?
          Did you see there? I'm not sure about complete information, but I hope that you'll find BKDG (BIOS and Kernel Developer's Guide) and GPU ISA manuals useful.
            • Full docs for CPUs chipsets and GPUs ?

              I did took a glance at some BKDG a while ago ( was it for K-8 ?) but because the text was very dry, I did not bother to really read it.

              I have opened  the doc you linked to ( Thanks !) and it seems that there might be some useful info there.

              Stil, it would be _very_ useful if AMD would stop hiding information if it is about to enable Open Sourcerers total access to its HW.

              It is painful to sift though thousands of pages of various user manuals and guides as it is, without having to guess value of hidden data...


            • Full docs for CPUs chipsets and GPUs ?
              What do you mean "the text was very dry?" It is not a poetry, it's a hard(ware) prose .
              About the AMD chipset's documentation: I don't think that AMD is hiding it, because, perhaps, it does not exist in more-less readable form (I mean for public use). I just can't see another reason .
                • Full docs for CPUs chipsets and GPUs ?


                  Originally posted by: avk What do you mean "the text was very dry?" It is not a poetry, it's a hard(ware) prose .

                  I mean, it reads as if it were phonebook.

                  No extra information, no example etc and on quite a few places information is insufficient.

                  It sems like it is expected from reader to have some basic knowledge, perhaps by reading some other not-yet-puublicly-released document.

                  Few examples:

                  page 21: Table of supported features:


                  Whet the heck is "triple plane compatible" and why is it even listed, if it isn't neither supported nor planned for removal ?

                  And why would some feature be removed - I mean if they plan to remove something, at least short explanation would be in order.

                  Page 22:

                  They say that each HT link can be configured either as coherent or non-coherent. That directly contradiscts Phenom's specs -which say that Phenom doesn't have any coherent links and so can't be used in SMP NUMA machines.

                  Look at the figure 2/page23:

                  There is 4-CPU configuration with one being labeled as BSP and other 3 as AP.

                  Text under pic states:

                  "The processor that is connected to the IO Hub is the BSP. "

                  All of them are connected just to "I/O device", nothing else.

                  It is unclear how the CPU "knows" which role should it play- is some kind of HT link linkage discovery done automatically just after reset ( but thisdoesn't seem logical, since links have to be setup later in separate, special procedure ), is there special pin for that purpose or something completely different ?

                  Also, there is much talk about PVID/SVID etc, but without basics.

                  I seem to remember something within Intel's literature about 5-6 VID pins and some kind of protocol through which CPU sets up desired voltage on VRM, but here there are just some details without whole picture.

                  It seems that CPU has provision for some kind of protocol negotiation ( as in parallel/serial ), but everthing else seems hazy...

                  The list goes on and on...


                • Full docs for CPUs chipsets and GPUs ?
                  Well, I think that this is a common culprit of many technical documents which are not supposed to be read by many people. Perhaps, you would need to contact directly to somebody at AMD for some answers. Hey, AMD, is anybody home?