I did took a glance at some BKDG a while ago ( was it for K-8 ?) but because the text was very dry, I did not bother to really read it.
I have opened the doc you linked to ( Thanks !) and it seems that there might be some useful info there.
Stil, it would be _very_ useful if AMD would stop hiding information if it is about to enable Open Sourcerers total access to its HW.
It is painful to sift though thousands of pages of various user manuals and guides as it is, without having to guess value of hidden data...
What do you mean "the text was very dry?" It is not a poetry, it's a hard(ware) prose .
About the AMD chipset's documentation: I don't think that AMD is hiding it, because, perhaps, it does not exist in more-less readable form (I mean for public use). I just can't see another reason .
Originally posted by: avk What do you mean "the text was very dry?" It is not a poetry, it's a hard(ware) prose .
I mean, it reads as if it were phonebook.
No extra information, no example etc and on quite a few places information is insufficient.
It sems like it is expected from reader to have some basic knowledge, perhaps by reading some other not-yet-puublicly-released document.
page 21: Table of supported features:
Whet the heck is "triple plane compatible" and why is it even listed, if it isn't neither supported nor planned for removal ?
And why would some feature be removed - I mean if they plan to remove something, at least short explanation would be in order.
They say that each HT link can be configured either as coherent or non-coherent. That directly contradiscts Phenom's specs -which say that Phenom doesn't have any coherent links and so can't be used in SMP NUMA machines.
Look at the figure 2/page23:
There is 4-CPU configuration with one being labeled as BSP and other 3 as AP.
Text under pic states:
"The processor that is connected to the IO Hub is the BSP. "
All of them are connected just to "I/O device", nothing else.
It is unclear how the CPU "knows" which role should it play- is some kind of HT link linkage discovery done automatically just after reset ( but thisdoesn't seem logical, since links have to be setup later in separate, special procedure ), is there special pin for that purpose or something completely different ?
Also, there is much talk about PVID/SVID etc, but without basics.
I seem to remember something within Intel's literature about 5-6 VID pins and some kind of protocol through which CPU sets up desired voltage on VRM, but here there are just some details without whole picture.
It seems that CPU has provision for some kind of protocol negotiation ( as in parallel/serial ), but everthing else seems hazy...
The list goes on and on...
Well, I think that this is a common culprit of many technical documents which are not supposed to be read by many people. Perhaps, you would need to contact directly to somebody at AMD for some answers. Hey, AMD, is anybody home?
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