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Adept I
Adept I

SMI problem on AMD Epyc 7301

Hello!

I'm working with AMD Epyc 7301 (AMD64 Family 17h model 00h-0Fh) with QNX (real-time OS) and have SMI interruptions on all CPUs every 32 ms for ~400 us. But in Linux (SLES RT) i dont't see such behaviour and the SMI counter in MSR results 0. I've read Performance Tuning Guidelines for Low Latency Response on AMD EPYC™-Based Servers Application Note and perform all BIOS optimization to decrease or remove SMIs, but it didn't work in this case. 

So, I have some questions:

1. Is there a way to disable SMI or sources of SMI in MSR or other specific registers, that I can write from OS?

2. Do you have any suggestions what can be a reason for such behaviour?

3. In case if you known with this promlem, what should I do to reduse SMIs in QNX like it works in Linux?

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Adept I
Adept I

Re: SMI problem on AMD Epyc 7301

In case that someone face the same problem. 

There is an SMI register space describred in BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 16h Models 00h-0Fh Processors doc on p. 875. And I found SMI Enable bit in SMITRIG0 register. Setting this bit disables SMI. Also there is a possibility to disable SMI sources.

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Journeyman III
Journeyman III

Re: SMI problem on AMD Epyc 7301

Hello,

I observed a similar behavior. I am using a Supermicro AS -1023US-TR4 Server with two AMD Epyc 7501. I am doing operating systems research. However, I think you need to read the SMI count out of the PMC registers. Reading of SMI count is (as far as I know only supported on non-AMD AMD64 platforms). You can configure a PMC to count SMIs, I am doing this and get reliable information when SMIs occured. Sadly they occur really often and polute my measurements quite often.

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