Hello AMD Community,
Given that the PCIe controller is integrated inside the CPU, the chipset also provides PCIe lanes and the connection between the CPU and the chipset is also PCIe, I would like to ask the following:
- Where is the PCIe root complex? Is it inside the CPU?
- Since the CPU and the chipset (B550) are connected via PCI x4 link, it makes me think that a lot of chipsets should contain a PCIe switch that provides the additional downstream lanes?
- If 2. is correct, can I get some code samples to use the PCIe switch for peer-to-peer communication between endpoints?
