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Journeyman III

How to read DRAM accesses Hardware counter on Family17h?


   I am working on performance analysis of an application running on Family 17 processor, and I want to characterize some threads as memory bound, or L3 cache bound or L2 cache bound. To this end, I need to read Hardware performance counters, in particular NBPMCx0E0 DRAM Accesses from BKDG-Family15h

  On the recent family 17h, we don't have this register, rather we have Data Fabric performance counters I believe. I am referring to PPR for Family 17h NDA version.

Could you please let me know how we could access such performance counters on the new family processors? Also, currently I am using Linux perf to access raw counters using rNNN syntax. And I hope the counts I get can be "believed" keeping in mind that AMD has not delivered much code into perf for Family 17h.

PS: The threads are currently pinned to cores. So, in essence, if I read per-core event, I would be reading per-thread.

Update 1

Just tried AMDuProfCLI. I am glad that AMD has something perf like for the family 17h. I see a set of PMC events, which are all wonderful. But, I am direly in need of L3 counters and DF counters.

Would be glad if someone could direct!



1 Reply

Re: How to read DRAM accesses Hardware counter on Family17h?

Hi Pramod,

The latest v3.2 version of AMDuProf has AMDuProfPcm utility will help you to monitor some of the predefined L3 and DF metrics. Refer chapter 9 in User Guide