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Journeyman III
Journeyman III

Alternative to TLB flush through IPI?

Is there a possibility to invalidate TLB entries on another CPU?

I use many threads in the same Addressspace. Due to the application design i have to page in and out a lot. Every time i do so the TLB of my thread and the other threads need to be invalidated. Is there another way to invalidate the TLBs / particular entries in the TBL without sending an Interrupt to all affected CPUs?

I'd like to send a INVLPG throuch the APIC to another CPU without disrupting their work.

for a quadcore it maybe was ok, but if i have in the future 64 cores running and everys time i change a page the cores have to invaldiate that page by hand in 64 CPUs or - even worse - flush the whole TLB then i expect a better solution.

best regards

Dennis

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3 Replies
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Re: Alternative to TLB flush through IPI?

Hello chaoscode‌,

I'm afraid we do not have a way to do what you're looking for.

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Journeyman III
Journeyman III

Re: Alternative to TLB flush through IPI?

Hi mbaker_amd

Seems like one of my prayers have been heard.

in https://www.amd.com/system/files/TechDocs/24594.pdf  Rev. 3.31—October 2020 is on page 427 the instruction

INVLPGB Invalidate TLB Entry(s) with Broadcast is listed.

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Re: Alternative to TLB flush through IPI?

Great, so glad that works for you.  

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