If the L3 cache in the diagonal direction is interlinked, then all the cores need to go through up to two L3 cache intervals for inter-core communication.
Well, I think a 6 core CCX is a lot more likely as AMD's 'Starship' Processor is supposed to feature 48c/96t 6 Core CCX * 2 = 12. 12 cores per die for a total of 4 dies per starship processor would equal 48. I don't think AMD is going to jump ahead of themselves here as there is no reason. Especially, since Intel 7nm are roadmapped for 2020.