With the introduction of the EPYC with more than 32 Cores / 64 Threads, my project CoreFreq is impacted to face such a high number of CPUs.
Can we say than a 64 bits architecture is de facto limiting the number of physical Cores to 64 ?
Can we say than a 64 bits architecture preserve any memory atomic operation to a quad word ?
What is the most discriminant definition of 64 bits ? The size of the cache line queried from cpuid ?
Other thoughts ?
Impacted source code
I'm using asm atomic operations for several purposes:
Where each CPU, based on its number, is assigned a bit location in quad-word. This allows simple atomic comparaisons for instance.
Issue: with a 128 SMT cores Processor, the 64 bits memory and register involved in atomic operations are not "long" enough to store all CPUs.
...
64bits supports up to 256 cores
64bits means that the cpu uses 64bit wide datapath, integer size and memory address widths
64-bit computing - Wikipedia
Caps and Limits on Hardware Resources in Microsoft Windows and Red Hat Enterprise Linux – PADT, Inc....
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Thank you for these pointers.
I now have to find GP instructions with 256 bits operands that I can use in Kernel ...
Edit: so far, available for both AMD & Intel, the CMPXCHG16B instruction to compare RDX:RAX with m128.
Thus 128 CPUs
It represents another attempt by the Arm world to grab a chunk of the lucrative data-center server market, which is virtually 100 per cent locked up by Intel and its x86-64 Xeon bruisers mywegmansconnect
After searches, I'm closing subject with a 256 Core Count. Scaling CoreFreq up in progress ...