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MikaV
Journeyman III

Zynq™ UltraScale+™ (Cortex-A53) deadlock

Hi,

I'm running a single processor application on Cortex-A53 processor (The design based on Arm Zynq Ultrascale+ processor), and occasionally the processor ends up to a deadlock.

When connecting the JTAG, the running Cortex-A53 #0 target cannot be halted. Reading the registers while it is still running produce N/A for everything else, except for the PC. The PC is not random place, as it has been several times the same address, but not always. What I have noticed is 'DSB SY' command is always followed by the PC value. This is not very easy to reproduce, but with some software versions it happens more often than the others.

I'm after any ideas how this should be debugged as I cannot read anything from the running processor itself, but I can access the memory and peripherals via PSU/APU.

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MikaV
Journeyman III

One route to investigate this would be to configure CoreSight to trace all branches to ETF while running, and then those could be inspected after the hang. I think I was able to configure ETM #0 properly, but I faced a challenges to write the data to ETF. The configuration should be done via TMC register (https://developer.arm.com/documentation/ddi0461/b/Programmers-Model/Register-summary) and it is referred in (https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/TMC), but the address space doesn't contain TMC (https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/CoreSight-Address-Map).

And I cannot find that address referred from anywhere. Can anyone help on this or in the original problem?

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It turned out ETF1, ETF2 and ETR all are TMC registers, so that part is more clear now.

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