Yes that is PBO on, everything else untouched apart from the voltage offset. the max values appear to be the same as mobo limits yes (355/255/200)
Well you could be on to something there. Not sure why ASUS would set the EDC limit lower than the TDC, that doesn't really make any sense. The EDC is the max short term boost amperage the system will allow, and TDC is the max sustained. The board is telling the AMD algorithm that spikes on 200A are all it can handle, but do a sustained load at 255A?
I would make sure that the EDC is always higher than or equal to the TDC. Since the board has locked EDC at 200, bring TDC down to the same amount or below. I would just try 215/140/160 as I have set and see how your boost does with that.
I have been running 215/140/160 since you mentioned yesterday to see what the results are. unfortunately they are quite similar high temps although ever so slightly lower than previous and performance has taken a slight hit:
Single core I still don't reach 4.9GHz and temps are still ridiculous considering only a fraction of the cpu is being utilised and it still manages to reach the same temp as an all core load?
Thanks for the images.
I would set the scalar to 1X if it isn't already.
Also, under curve optimizer I would try to set Core1 and core 7 on CCD0 to -5, and all other cores at -10 (the numbering is often different in UEFI). Then set CCD1 to a flat -20. See if that helps at all.
I wonder if these ASUS boards are damaging themselves. Since they set the EDC to 200A, that would imply that only a short term spike at 200A is acceptable for the VRM design, but a sustained load up to 255A is fine? One of those limits clearly isn't correct. I may have avoided that issue on my ASUS board as I set the limits manually. I am also running X470, and these strange limits may be specific to 500 series boards. Additionally, by CPU block also cools the VRMs, so it is hard to say how universal the issue is.
I like this approach. However, in my case I started seeing WHEA errors cropping up.
I have a Strix 570-E mainboard, so following the steps was pretty easy.
I was also experiencing random reboots when pushing the RAM to 1.35v and associated D.O.C.P timings.
I've gone back to my Ryzen Master profile. I get an all core speed of 4350 at 1.3V.
Oddly, I set the memory to be coupled at 1800 for both the memory and fabric clocks without the voltage bump to 1.35V. It seems to work fine, although the default timings are horrible (set to Auto) and nowhere near the timings you see if you look XMP values up.
Stability with good performance is what I'm looking for. Ryzen Master is pain to start every time but I think it's helped me increase the life of the CPU by not pushing extra voltage to get performance.
If I could find out how to apply this method successfully without WHEA errors, I'd like to revisit this method.
You could try the following RAM timings at 1.35V and 3600/1800.
That has been working for me, although they are fairly loose. Turn on PBO but set it to default limits (142W 95A 140A) for a 105W TDP processor. Do you still get errors then?
Using just the PBO settings mentioned, no WHEA errors. Using Ryzen Master to monitor.
Multi-core Cinebench R23 test showed all core running at 4113 ish for a score of 13673.
Average temp was 70C. Average voltage: 1.36907V
SMT is disabled. Single core was running about 4500. Temp was averaging 60C. Peak voltage was 1.47V. Cinebench score was 1326.
So it would appear in my case, I would be surpassing the 1.3V just using the default settings for the 105W TDP.
Just had time to do the quick test at lunch. Will look into the RAM settings. Thanks!
pretty sure the best cores on both ccx's are -12 the 2nd best are -20 and the rest are -25. Can't confirm quite yet but its thereabouts. The scaler will be set to auto at the moment though, I have tried 1x in the past with seemingly no benefits.
Will confirm values later and try 1x scaler again and get back to you.
It is worth mentioning that the best cores on CCD1 are often worse than all the cores on CCD0. So I usually keep CCD0 with a higher offset than CCD1.