If we had to guess, it should be because TR and TR+ both have two dies with that have memory controllers on them, and the new system Has one I/O die with a unified memory controller. The pin layout would need to change going from 2 areas for memory controller to 1.
It can only be beneficial in the end, as the socket will be more specifically designed for that system. Ryzen was still a 1 to 1 change so they could get away with it.
