Processors

[agner]

Please make the BIOS guide for Ryzen available, even if just a draft. Need information on performance monitoring.

[gc9]

(While we are all waiting, here's a 2013 note that hints at how complex it can be to verify and document how to best use performance counters:

  John McCalpin's blog: Notes on the mystery of hardware cache performance counters​

)

[gc9]

Two related manuals were updated this week.

• AMD64 Architecture Programmer's Manual Volume 2: System Programming
• AMD64 Architecture Programmer's Manual Volume 3: General Purpose and System Instructions

Tech Docs

Performance monitoring is covered in some relevant chapter and appendix sections of Volume 2:

13 Software Debug and Performance Resources

13.2 Performance Monitoring Counters

13.3 Instruction Based Sampling

13.4 Lightweight Profiling

A.6 Performance Monitoring MSRs

Change history related to performance monitoring:

Retired Performance Counter:

The Volume 2 revision history says

"Added Instructions Retired Performance counter in Section 13.1.1."  (Typo.

The short addition is in Section 13.2.1, page 370, with margin changebar.)

(Section 13.4.2.2 also discusses the instructions retired counter.)

This MSR address, C000_00E9, is not listed in Appendix A.1 (MSR by address) nor A.6 (Performance monitoring MSRs).

L2 Cache

(Volume 2 Appendix A.6 lists MSRs C001_023x to specify/count L2 cache events.  These are listed in Jaguar Family 16h BKDG but not Bulldozer Family 15h BKDGs, so might be new for software that previously targeted Bulldozer.  Also discussed in section 13.2.1 on page 370.)

Time stamp counter

The Volume 3 revision history says

"Modified RDTSC and RDTSCP."

Sections RDTSC and RDTSCP have changebars on the paragraph that says the TSC is implementation-dependent and may be affected by power management frequency changes, and to consult the BKDG for your product.

[volume 2 section 13.2.4 also discusses serialization of RDTSCP with respect to other instructions.]

References to product BKDG for implementation-specific restrictions:

Sections 13.2 and 13.3 refer the reader to varying products' BIOS and Kernel Developer's Guide (BKDG) for:

• "Support for the extended performance monitoring registers[,] and the performance-related events selectable via the *PerfEvtSel registers[,] vary by implementation"
• "Maximum CNT_MASK value (in the range FFh:01h[)] is implementation dependent"
• "In some implementations, support for a specific EVENT_SELECT value may restricted to a subset of the available performance counters."
• "For more information on the defined fields within the NB_PerfEvtSeln registers"
• "For more information on the defined fields within the L2I_PerfEvtSeln registers"
• "The IBS Op Data 2 Register captures northbridge-related performance data. The information captured is implementation-dependent."

[agner]

Thank you. But I still need the BIOS guide for a list of performance events.

[gc9]

AMD posted initial Ryzen Model Specific Register (MSR) documentation to Tech Docs this week in the form of

• "Processor Programming Reference (PPR) for AMD Family 17h Model 01h Revision B1 Processors".  Thank you AMD.

Section 2.1.13 Performance Monitor Counters contains the PMC details.

---

A comparison pass shows many differences across family/model 17h/00h PPR, 16h/30h BKDG, 15h/70h BKDG (spreadsheet attached).

• Only about 24 PMCs appear to be the same across all three architectures.
• About 4 more are similar between Ryzen and Excavator (Bulldozer family).
• Many counters are described only with a name in the PPR.
• Notably, Ryzen introduces two counters for L3.
• The L2 counters look completely different from those in family 15h and 16h.

Many counters are presumably omitted from this edition of the PPR:  no counters for interrupts, dispatch stalls, breakpoint hits, northbridge, crossbar, memory controller (nor infinity fabric).

But there might be enough to get started learning about Ryzen performance counters.

[agner]

Thank you. The Processor Programming Reference seems to have all the information about performance monitoring.

The Ryzen has a new core clock counter, which is exactly what I had hoped for. It is called "Actual Performance Frequency Clock Count (APERF)". This makes it possible to get consistent and reproducible clock measurements while the clock frequency keeps changing. Unfortunately, the APERF counter cannot be read with the RDPMC instruction in user mode, only with the RDMSR instruction in privileged mode. This makes it difficult to measure the performance of small pieces of code. You have to read the time stamp counter (TSC) and the APERF over a longer interval to calculate the core clock frequency, and then measure the test code with the TSC and multiply it with the ratio of the two clocks. It is easier with Intel processors where you can read the core clock counter with RDPMC in user mode.

[ivan_83]

I want to read processor temperature, but all known interfaces does not work now.

Could you provide some information about this?

[ivan_83]

Is there some short "howto" instruction to read temperature and use watchdog on 17h?

(I dont need whole BKDG 17h right now.)

[mona2017]

Dear gc9, dear AMD staff,

unfortunately, months after the Ryzen release, we still do not have sufficient details to understand how to retrive and to interpret CPU sensor readings. Could you please have a look at this record on LM-Sensors issue tracker and see which information you can make available to help your paying customers retrieve this information without a need to sign NDAs?

Support for AMD Family 17h Processors · Issue #16 · groeck/lm-sensors · GitHub

Thank you.

[gc9]

For Ryzen temperatures on Linux, a web seach turned up

https://linuxconfig.org/monitor-amd-ryzen-temperatures-in-linux-with-latest-kernel-modules