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OpenCL

himanshu_gautam
Grandmaster

Re: Unexpected Cache Hit statistics

Hi Lihan,

That was surprising and useful. How do we get L1 cache hit ratio?

Is there any counter for it?

Thanks,

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lbin
Staff
Staff

Re: Unexpected Cache Hit statistics

Currently, there is no L1 cache counter exposed.

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zenome
Journeyman III

Re: Unexpected Cache Hit statistics

Thank you Lihan for the insights.

But I really can not get my head around the cache hits I am observing, even after considering it to be L2 cache. Would be really helpful if you can shed some of your expertise (simple microbenchmarks: http://devgurus.amd.com/message/1287539#1287539). Could this be possible because of some weird way of calculating L2 cache hits ?

Himanshu: Thanks! Bringing in multiple lines on a miss could be a possible (though not entirely convincing, given the coalesced accesses). Btw the shared L1 cache is only for scalar data and instructions. Vector L1 Data cache is tied to One per CU.

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