OpenCL

[acekiller]

Recently, I am happy to see the OpenCL 2.0 support (drivers and SDK) released by AMD on Kaveri APUs. However, I have some questions about those features that maybe someone could help me.

1) I am not sure how pipe is implemented on AMD platform. I mean, on other platform such Altera FPGA, pipe is implemented at hardware level (registers) so the performance is very good. On AMD platform, is it a hardware capability or just a software-level function provided by drivers?

We want to know more details about pipe implementation because we care about the performance. From some benchmarking results, we found that Pipe may be a cache favored component.

2) I noticed that there are quite a lot OpenCL 2.0 features (pipe, dynamic parallelism and so on) not supported on AMD CPUs. That is a pity for a real HSA platform. Is there a timetable for the support on the CPU also?

Hope anyone can help in this case.

[dipak]

1) AFAIK, on AMD platform, pipe is just software implemented feature.

2) None that I know of.

Regards,

[maxdz8]

Following.

I've read somewhere AMD CL pipes are global memory in nature - perhaps mapping to the "append/consume buffers".

I hope they'll move them to GDS/LDS somehow. They're most likely not registers.

Just to be clear, that's just speculation by me.