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[yhwan]

Hello, I'm working with Carrizo APU (GCN3). I'm trying to figure out how I can flush GPU's cache so that cached data in GPU is explicitly flushed to physical memory (which will let CPU see the updated value). By going through GCN3 instruction manual, I found assembly instructions that write back L1 (s_dcache_wb) and scalar data cache (s_dcache_wb_vol). However, I couldn't find any information on how to flush L2 cache. Is there any instruction or way to explicitly flush GPU's L2 cache? Thank you!

[dipak]

Hi,

If you're simply asking about the ISA instruction, then no. As I checked, there is no ISA instruction to flush the L2 cache.

Knowing the usage may help us to provide more information in this regard. Say, if SVM atomics are used on fine-grained SVM, then, the host or CPU can see the modifications done by GPU device(s).

Regards,