As posted earlier on the AMD Community forum
o] 1.0
What I have is this:
[o] building processors with a capacity to perform multiplication (and other operations) across operators
Conventionally, we can have
core1: ADD x,y
:=x+y
BUT we CAN have also an operation on a core or plural cores
ie core1 : ADD x,y (arbitrary x,y)
core2 : ADD x,y (arbitrary x,y)
core3 : MUL core1:ADD,core2:ADD
This yields
:= a super ADD structure which extends into the CPU adder and back out to the output
MUL core1:ADD,core2:ADD := ADD^2 (as there are 2 cores)
:. core3 could accept ADD^2 operands, or x,y,x,y
What's this look like in practice?
For
x=2,y=3 :
core3 : MUL core1:ADD x,y , core2:ADD x,y
:=x+y[+]x+y
:=2+3+2+3
:=10
Note: [+] is because MUL ADD honors addition (cf. x^2+y^2, := 13 which is not correct)
That is, we simply must do it this way to honor the original operator, ADD
If we go back and do this conventionally
core4:ADD 2,3
:=5
core 4: ADD 2,3
:=5
and then to combine an extra step,
core4: ADD 5+5
:=10
OK, so we can operate on operators and obtain a good output.
So far, not that big a deal...
If we discover a new operator, XMUL:
core3:MOV CX,4
XMUL core1,core2
We can now operate on core1 and core2 n times (in this example CX, which describes the number of multiple operations to perform by a subsequent XMUL, is 4)
If core1 and core2 are the same as before, ADD x,y, each, and CX in core3 is 4:
core3:XMUL core1,core2
yields
x+y[+]x+y[[+]]x+y[+]x+y[[+]]x+y[+]x+y[[+]]x+y[+]x+y
:=5+5+5+5+5+5+5+5
:=40
This can be done conventionally with a loop structure of ADD and MOV
MOV DX,0
:addloop
ADD x,y
MOV CX, [address]
INC DX
SUB DX,4
JNZ addloop
which is 6X4=24 operations.
Better.
We can describe any value that will fit in a register for XMUL though. Consider 256, or 1024 or a million.
BUT you may well ask, why bother... we could just do MUL 5,8 :=40, right?
The point really is that
operators can in fact be made to operate on each other
The code takes longer to write at first, I would think, but once a compiler is designed to accept the code even conventional code may be optimisable considerably (this is beyond my skill to discover : )
[o] 2.0
[o] In a CPU a clock signal has a rising edge, a pulse with a period, and a falling edge.
eg., 100MHz
_________/---------------\____________
I am suggesting that a clock pulse can be superimposed over this conventional clock signal,
one with a higher frequency
eg., 1GHz
/\/\/\/\/\/\/\/\
_________/---------------\____________
How could this work?
The conventional clock is within standard transistor design parameter
The new clock pulse can raise and then ground the transistor whilst the conventional clock signal maintains the transistor at conventional operation
There is no reason why a circuit in a conducting transistor cannot itself be switched by an external clock signal at a higher frequency.
The transistor does not need to actually do the switching to produce a circuit, providing the supporting bus and interface to memory can keep up with the higher clock frequency.
Expensive in dollar terms though these higher frequency interfaces may be, in terms of processing cost they can be very efficient
