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HSA

humasama
Adept I

Address mapping of memory controller on Kaveri

Does anyone know any details about memory controller or address mapping schemes of Kaveri?

How does memory controller translate physical address on Kaveri? Are bit0~bit2 byte offset?

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bridgman
Staff
Staff

Re: Address mapping of memory controller on Kaveri

I couldn't find an explicit statement in the BKDG but almost everything I read was consistent with address bits 0-2 corresponding to bytes within a 64-bit chunk going out on the memory bus.

That said, there was one statement about interleaving even and odd bits in section 2.9.6 (DRAM Data Burst Mapping) which I didn't fully understand (it talks about even/odd bits but also about mapping them to 64-bit quadwords) that might be an exception but not sure.

http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf

JB