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[rotor]

Hi guys,

I am using a a Lookup Table(LUT) for my kernel and just bump up with a question about how the GPU cores access a common memory location like a LUT?

I am considering this scenario: I have a lookup table LUT which is located somewhere in global memory and during the execution time my threads repeatedly access this LUT to refer to some result (lets say refer to the LUT through 2D indexing LUT). Now the question is: what happens if there are 100 cores(computational units) access this LUT at a same moment? Will the cores have to wait in a queue or smt like that to access this LUT since they are refer to the same memory object? If they don't have to wait in line for accessing LUT, how does the GPU memory controller handle this? especially in the case that 100 cores refers to 100 different element of the LUT, how does the GPU's address decoder unit work? Is there any special architecture inside the GPU that allows the cores to share the same memory bus?

Thanks,

Roto

[Byron]

Please read DirectCompute presentation from GDC 2010 located at http://developer.amd.com/documentation/presentations/Pages/default.aspx

[rotor]

Hi Byron,

Thank you very much for the link. It really helpful. I would recommend other ones look at it, there are lots of technical issue addressed there.

However I am not very clear about a point in the slide TGSM Performance (2): it said that using a padded array/structures can help avoid bak conflict. E.x. using array[16][32] instead of array[16][33]. How could it avoid bank conflict?

Thanks,

Roto

[Byron]

If all the threads in the thread group access the exact same memory location in the Look-up Table, then no bank conflict will occur and performance will be kept normal.

However if different threads in the thread group access memory locations whose addresses are separated by 32 DWORD then the same bank has to be used to access those locations and therefore bank conflicts will occur, impacting performance considerably.