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bennicus
Journeyman III

problem with invariant TSC on "Phenom II 965 Black edition" (maybe other models too)

So... does this processor *actually* support invariant TSC or not?  I'm using CPUID 0x80000007 and checking EDX:8 for invariant TSC support and it returns that it does.  However the values I'm getting back from rdtsc definitely aren't invariant, they're jumping backwards and forwards all over the shop.  Is is falsely reporting invariant TSC support, or does "invariant TSC" mean something else on AMD processors? 

Cheers,

Ben

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avk
Adept III

It seems to me that the values you are getting back are from different cores. Have you set up affinity before RDTSC? If not, then please do something like this:

SetProcessAffinityMask (GetCurrentProcess (), 1);

As an alternative you could use another instruction, RDTSCP.

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So you think the invariant TSC (not regular rdtsc, though its the same instruction) can vary across cores?  That wouldn't be ideal but it's possible I suppose.  Unfortunately the documents don't seem to go into much detail on this, but on Intel machines it seems that the invariant TSC is the same across all cores - I guess either they share the same invariant timer, or the timer rates are the same on all cores (which it should be) and they all get reset at the same time (which they should be).

Even more unfortunately, for performance reasons I can't really use SetProcessAffinityMask() or even SetThreadAffinityMask() as I have multiple threads all calling timing functions regularly.  Also for performance reasons I can't use RDTSCP, as that is a serializing operation (i.e. it stalls the CPU and flushes the instruction queue), at least according to http://developer.amd.com/pages/1214200692_5.aspx.

I haven't been able to find any other documentation about RDTSCP or invariant TSC on AMD, if you know of any other links I would be very grateful.

I am basing most of my limited knowledge off this document: http://www.intel.com/Assets/pdf/manual/253668.pdf , and experimental results.  Have you seen any equivalent documents for AMD processors?

 

Thanks

Ben

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As far as I can see, those just give the same general description of invariant TSC that you find everywhere:

"If CPUID 8000_0007.edx[8] = 1, then the TSC rate is ensured to be
invariant across all P-States, C-States, and stop-grant transitions"

I did notice they also say "The processor sets the counter to 0 upon reset", so unless different cores are reset at different times, or the rate of the invariant TSC is different between cores, then it should actually be synchronised across all cores, same as on the Intels.

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Sorry, I don't know what to say... What about Cool&Quiet technology? Have you disabled/enabled it in BIOS and/or Windows?

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