All,
I would like to know the size of the intermediate victim cache that sits between the L1 (D) and L2 caches for both the Athlon and Opteron hardware. I also would like to establish whether the L1 (I) has a separate victim came or it shares the victim buffer with L1 (D).
Thanks in advance for your help
All,
Excuse the typo in my earlier query - below is the edited message I'm resending.
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I would like to know the size of the intermediate victim cache that sits between the L1 (D) and L2 caches for both the Athlon and Opteron hardware. I also would like to establish whether the L1 (I) has a separate victim cache or it shares the victim buffer with L1 (D).
Thanks in advance for your help
I think the only way to know it is to test you CPU(s) by yourself.
IIRC this is in the optimization manual, it's 8 cache lines (1024 bytes), I'm not sure but I think this is for both I$ and D$.
Are VBs provided between L2 & L3 caches and between L3 cache & Sys memory? If so, what are respective sizes of the VBs?
Thanks for the suggestion - but if I can ask further, which procedure(s) exactly do I have to invoke in order to test the VB sizes on the K8 CPU architecture?