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cadorino · ‎08-23-2012

Hi to all,

I run the GlobalMemoryBandwidth sample on a AMD 7970 and the results is the following:

Platform 0 : Advanced Micro Devices, Inc.

Platform found : Advanced Micro Devices, Inc.

Selected Platform Vendor : Advanced Micro Devices, Inc.

Device 0 : Tahiti Device ID is 005EF838

Build Options are : -D DATATYPE=float4 -D OFFSET=16384

Global Memory Read

AccessType : single

VectorElements : 4

Bandwidth : 1672.16 GB/s

Global Memory Read

AccessType : linear

VectorElements : 4

Bandwidth : 1756.49 GB/s

Global Memory Read

AccessType : linear(uncached)

VectorElements : 4

Bandwidth : 220.769 GB/s

Global Memory Write

AccessType : linear

VectorElements : 4

Bandwidth : 501.668 GB/s

The question is: how can the linear read bandwidth be over 1 terabyte per second is the max theoretical bandwidth is about 260 GB/s?

The question that naturally follows is: are global buffer reads cached?

Thank you very much!

dmeiser · ‎09-04-2012

No, that's a cache hit.

A typical cache contention situation would be the following:

-wavefront 1 reads data from global and brings it into cache

-subsequently wavefront 2 reads data from global, brings it into cache and evicts wavefront 1's data from cache

-then wavefront 1 will have to read again from global memory (its data is no longer in cache).

If only one wavefront is running on a compute unit the second read by wavefront 1 would be cached.

If you anticipate that cache contentions like that are a performance limitation in your code you can limit the number of wavefronts executing on any CU by allocating so much shared memory that only one wavefront fits on a CU.

On the other hand, when lots of wavefronts access the same data you can get huge effective bandwidth gains by having many wavefronts execute on the same CU. Many of their reads will then be cached.

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Strange global memory bandwidth for HD 7970