SR provides a limited form of sharing. They're called "shared_temp" in IL, see dcl_shared_temp.
On most GPUs where the wavefront size is 64 there will be 64 distinct SRs, all called "SR0". If there are 150 wavefronts executing on the SIMD (e.g. 7 at any one time) then they will all share the declared SRs.
Sharing is by lane and there are 64 lanes in each wavefront. So for example lane 3 has "SR0" which is shared by all 150 wavefronts. Lane 4 has "SR0" that is separate, but also shared by all 150 wavefronts.
You can define multiple SR registers, so if you have 2 defined, then the total population of SRs that are reserved on the SIMD core is 128. This will provide SR0 and SR1 and for each of the 64 lanes.