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fesc2000
Adept I

OpenCl 2.0 FIFOs/pipes

Hi,

i just read about pipes introduced with OpenCL 2.0.

I see a lot of use cases for this, like streaming data though several kernels running in parallel.

But i wonder whether there is a chance that this is going to work with good performance in current hardware ... or is it just a software abstraction.

I know that for example packet processing engines/CPUs spend a lot of silicon and extra features for this (e.g. to dequeue FIFO entries to several processing elements and enqueue the results in the correct order again).

Any comments from AMD?

Thanks,

Felix.

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5 Replies
himanshu_gautam
Grandmaster

Re: OpenCl 2.0 FIFOs/pipes



I see a lot of use cases for this, like streaming data though several kernels running in parallel.


But i wonder whether there is a chance that this is going to work with good performance in current hardware ... or is it just a software abstraction.



That is for time to tell. This is just a provisional spec from khronos. If vendors find it useful to implement it in hardware, they may consider it. But there is a long way to go for that. Pipes are really interesting to me too, as many networking domain applications may benefit from them.

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himanshu_gautam
Grandmaster

Re: OpenCl 2.0 FIFOs/pipes

This use-case may not be for GPUs -- but you never know..

But the more baffling part is that the spec does not list which built-in functions one should use to read and write packets into pipes... 😞

Did you guys find it?

-

Bruhaspati

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himanshu_gautam
Grandmaster

Re: OpenCl 2.0 FIFOs/pipes

Found it in OpenCL C specification. Check Properly the spec has been divided into three documents: OpenCL, OpenCL C, and OpenCL extensions.

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fesc2000
Adept I

Re: OpenCl 2.0 FIFOs/pipes

Maybe it's meant for DSPs, i heard TI wants to support OpenCL ..

thesmileman
Journeyman III

Re: OpenCl 2.0 FIFOs/pipes

TI already has beta OpenCL drivers for some of their DSP server-focused parts.

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