As processors get more and more complex in order to be backward compatible, I sat and thought for a few,
and came up with a simple outline for one.
Idea for processor outline.
1 reg for code begin
1 reg for code end
1 reg for code instruction size ( 8 / 16 / 32 / 64 )
1 reg for IP
( auto mechanism to cmpare IP to code begin / end )
( so code pointer can never go beyond its bounds )
1 reg for stack begin
1 reg for stack end
1 reg for stack stepping ( 8 / 16 / 32 / 64 )
1 reg for SP
( auto mechanism to cmpare SP to stack begin / end )
( so stack pointer can never go beyond its bounds )
1 reg for data begin
1 reg for data end
1 reg for data stepping ( 8 / 16 / 32 / 64 )
1 reg for DP
( auto mechanism to cmpare DP to data begin / end )
( so data pointer can never go beyond its bounds )
( 1 for / next reg )
1 reg for initial val
1 reg for end val
1 reg for increment val
1 reg for current val
32 variable registers
Variable regs have an upper and lower buss connecting them.
So reg / reg swaps can be done in one clock cycle 1 transfers on the top buss 1 on the lower.
Variable regs upper and lower busses run to both the INTEGER and FPU input regs.
So two var regs can appear at the math input at the same time.
( probably implemented as side by side busses )
( this would make reg / reg instructions possible. )
1 double wide reg ( Accumulator ) for Int_math / FP_math unit output.
Global Programs descriptor table regs
1 reg for memory start for loading programs
1 reg for memory end for loading programs
( Auto compare curcuit to compare attempted access beyond lower / upper bounds. )
Kernel descriptor table regs
1 reg for kernel memory start.
1 reg for kernel memory end.
Drivers descriptor table regs
1 reg for Drivers memory start.
1 reg for Drivers memory end.
( This allows the Kernel / Drivers to isolate themselfs from programs. )
( And allows the Kernel to be isolated from third party drivers. )
Probably an adjustable address hardware NMI to give the kernel oversight of the memory and hardware accesses.
