Any information about M9 adaptive deinterlacing is requested
It seems that in xf86 code adaptive interlacing is enabled by setting bit 12 (OV0_ADAPTIVE_DEINT) of OV0_SCALE_CNTL register. However, OV0_ADAPTIVE_DEINT_OFFSET register is not mentioned anywhere. Is it required?
Does anybody know the exact procedure to enable adaptive deinterlacing on M9?
